1. Field of the Invention
The present invention relates to a thin film semiconductor device having a plurality of thin film transistors (abbreviated as “TFTs”) formed on an insulating substrate, and a method of manufacturing thereof. More particularly, the present invention relates to a thin film semiconductor device provided with a plurality of kinds of TFTs which are formed on the same substrate and have gate insulating films different in thickness from each other, and a method of manufacturing thereof.
2. Description of the Related Art
An image display device of a flat panel type such as a liquid crystal display device or an organic EL display device has been used as a monitor for a notebook personal computer, a television or the like. The image display device of the flat panel type is characterized by a thinner shape and a lighter weight as compared with a CRT. In such the liquid crystal display device or such the organic EL display device, a display unit having pixels arranged in a matrix form on an insulating substrate such as an inexpensive glass substrate is formed by using a thin film forming technique. Further, a gate driver and a data driver which are semiconductor integrated circuits are externally provided. Signals in accordance with an image are supplied to the pixels through he semiconductor integrated circuits, and thereby an orientation of a liquid crystal molecule or an intensity of light emission of an organic EL is controlled such that the image is displayed.
In recent years, a polysilicon thin film can be formed on a glass substrate as the thin film forming technique has been improved. As a result, a thin film semiconductor device is put to practical use, in which a part of a drive circuit unit including polysilicon TFTs is formed on one and the same substrate together with a pixel unit. An operating voltage of such a drive circuit unit is desired to be lower from the view point of lower electric power consumption. On the other hand, a voltage higher than a predetermined value is required for a pixel operation. It is therefore necessary to form a plurality of kinds of thin film transistors having different operating voltages together on one and the same substrate.
In order to form a plurality of kinds of thin film transistors having different operating voltages together on the same substrate, a technique in which thicknesses of gate insulating films of the thin film transistors are varied in view of withstand voltage of the transistors is commonly used (see, for example, Japanese Patent Publication No. 2666103, Japanese Laid-Open Patent Application JP-P2004-253596A, Japanese Laid-Open Patent Application JP-A-Heisei 8-250742, Japanese Laid-Open Patent Application JP-P2003-332581A, and Japanese Laid-Open Patent Application JP-P2004-247413A). FIG. 1 is a cross-sectional view showing a thin film semiconductor device fabricated by a conventional technique. As shown in FIG. 1, island-like polysilicon films 3 serving as active layers of both of a low-voltage TFT and a high-voltage TFT are formed on an insulating substrate 1. Each of the island-like polysilicon films 3 includes a channel region 3c and source-drain regions. Formed on both sides of the channel region 3c are source-drain regions 3n of an n-channel TFT or source-drain regions 3p of a p-channel TFT. Each of the island-like polysilicon films 3 is covered with a first gate insulating film 4. A gate electrode 5 of the low-voltage n-channel TFT or the low-voltage p-channel TFT is formed on the first gate insulating film 4 over the channel region 3c of the island-like polysilicon film 3. Further, the gate electrode 5 and the first gate insulating film 4 are covered with a second gate insulating film 6. A gate electrode 7 of the high-voltage n-channel TFT or the high-voltage p-channel TFT is formed on the second gate insulating film 6 over the channel region 3c of the island-like polysilicon film 3. Moreover, an interlayer insulating film 8 is formed over all of the TFTs, and contact holes are formed to penetrate through the interlayer insulating film 8, the second gate insulating film 6 and the first gate insulating film 4. Formed via the contact holes are electrodes 9 being in contact with the source-drain regions 3n of the n-channel TFT and the source-drain regions 3p of the p-channel TFT.
According to the conventional technique, the source-drain regions 3n and 3p are formed without using any self-alignment method, or only the low-voltage TFTs are formed by using the self-alignment method while the high-voltage TFTs are formed without using any self-alignment method. Moreover, the channel region 3c of the TFT is a non-doped or a B-doped region, and the channel region 3c of the high-voltage TFT and the channel region 3c of the low-voltage TFT are formed to be the same doping state. Furthermore, Al or Cr or Si is used as the material of the gate electrodes 5 and 7, and the gate electrode 7 of the high-voltage TFT and the gate electrode 5 of the low-voltage TFT are made of the same material.
As for channel doping, a high-voltage transistor and a low-voltage transistor may be different from each other in a bulk type MOS transistor (see, for example, Japanese Patent Publication No. 2964232 and Japanese Laid-Open Patent Application JP-P2004-128487A). According to the Japanese Patent Publication No. 2964232, a channel region of a high-voltage n-channel MOS transistor is doped with an n-type dopant and a p-type dopant, while a channel region of a low-voltage n-channel MOS transistor is doped with only a p-type dopant. A channel region of a high-voltage p-channel MOS transistor is doped with an n-type dopant at a low density, while a channel region of a low-voltage p-channel MOS transistor is doped with an n-type dopant at a high density. Furthermore, the Japanese Patent Publication No. 2964232 also discloses another example, in which a channel region of a high-voltage n-channel MOS transistor is doped with a p-type dopant at a low density, while a channel region of a low-voltage n-channel MOS transistor is doped with a p-type dopant at a high density, and a channel region of a high-voltage p-channel MOS transistor is doped with an n-type dopant and a p-type dopant, while a channel region of a low-voltage p-channel MOS transistor is doped with only an n-type dopant.
Japanese Laid-Open Patent Application JP-A-Heisei 10-223909 discloses a semiconductor device, in which a conductive film having a work function different from that of material of a gate electrode is formed, and thereby a threshold voltage of a transistor is controlled.
FIG. 2 shows characteristics of the high-voltage TFTs and the low-voltage TFTs manufactured through the conventional method disclosed in the above-mentioned patent document: Japanese Patent Publication No. 2666103 and Japanese Laid-Open Patent Application JP-P2004-253596A. As shown in FIG. 2, there is a problem in that threshold voltages (Vth) of the high-voltage n-channel TFT and the high-voltage p-channel TFT are higher than those of the low-voltage n-channel TFT and the low-voltage n-channel TFT, respectively. Here, the threshold voltage (Vth) is a gate voltage with which a sufficient current begins to flow between the drain and the source of the transistor. It should be noted in the present specification that the low and high threshold voltages do not mean small and large absolute values, respectively. Unless not specially noted, a value on the more positive side is referred to “a higher voltage (or a larger voltage)” and a value on the more negative side is referred to “a lower voltage (or a smaller voltage)” in the specification of the present application. Here, the above-mentioned problem cannot be solved even when the manufacturing method described in the Japanese Patent Publication No. 2666103 is adopted, because a difference in the threshold voltage between the low-voltage p-channel TFT and the high-voltage p-channel TFT is undesirably increased.
For example, a peripheral drive circuit of a liquid crystal display device consists of digital circuits which manage two voltages at low level and high level. It is therefore desirable that a TFT is turned off at the time when the gate voltage is 0 V and also a sufficient drive current is obtained with a gate voltage of a small absolute value. In other words, it is desirable that the threshold voltage should not be so close to 0 V and should not be much away from 0 V. The reason is that an electric power consumption by the circuit during standby time increases in a case where the absolute value of the threshold voltage is extremely small, while a sufficient current driving ability cannot be achieved with a predetermined gate voltage in a case where the absolute value of the threshold voltage is large, which causes a deficient operation due to signal delay. According to the conventional characteristics shown in FIG. 2, a leak current in the high-voltage p-channel TFT at the time of the O-level signal may become large since the threshold voltage is 0 V, while the driving current of the high-voltage n-channel TFT may become insufficient since the threshold voltage is as high as 6 V.
The reason why the threshold voltage of the high-voltage TFT becomes high (i.e., shifts to the positive side) is that a carrier is captured by a recombination center which is generated in a forbidden band due to contamination in the gate insulating film of the high-voltage TFT and crystal defect in the channel region of the high-voltage TFT. More specifically, the contamination is caused by residual of the gate etching for the gate electrode of the low-voltage TFT. Also, the gate insulating film is damaged by plasma in a case of over-etching in the dry etching process for the gate electrode of the low-voltage TFT. Moreover, the crystal defect is generated at a surface of the polysilicon other than a region covered by the gate electrode of the low-voltage TFT, because of irradiation with a laser beam or a lamp beam at the process for activating impurities implanted into the source-drain regions. As described above, the problem that the threshold voltages of the high-voltage TFTs of both channel types become higher than those of the low-voltage TFTs is peculiar to the thin film semiconductor device shown in FIG. 1, in which the island-like polysilicon films 3 are formed on the insulating substrate and further the first gate insulating film, the gate electrode of the low-voltage TFT, the second gate insulating film and the gate electrode of the high-voltage TFT are formed in order on the island-like polysilicon films 3.